Semiconductor apparatus with repair information control function

ABSTRACT

A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array configured to store and to transmit repair information through the global line, and a control unit configured to selectively enable or disable signal paths among the input/output terminal, the global line, and the fuse array according to an operation mode of the semiconductor apparatus.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean application number 10-2014-0071051, filed on Jun. 11, 2014, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments relate to a semiconductor apparatus, and moreparticularly, to a semiconductor apparatus with a repair informationcontrol function.

2. Related Art

A semiconductor apparatus may include a memory block, and the memoryblock may include a plurality of memory cells.

In many cases, a subset of the plurality of memory cells may includeredundant memory cells for replacing memory cells that may have a defect(hereafter, referred to as defective memory cells).

A test process may be used to detect a defective cell from among theplurality of memory cells.

An operation of replacing a detected defective cell with a redundantcell may be referred to as a repair operation. The repair operation mayinvolve replacing an address for accessing the defective cell with anaddress corresponding to the redundant cell replacing the defectivecell.

The repair information may be addresses for accessing defective cells.The repair information may be stored in fuse sets.

During normal operation, when an address received at the semiconductorapparatus from a device external to the semiconductor apparatus is oneof the addresses stored in the fuse sets, the received address may bereplaced with an address corresponding to a redundant cell. This enablesnormal operation of the semiconductor apparatus.

SUMMARY

In an embodiment, a semiconductor apparatus may include a global lineconfigured to enable electrical coupling between a memory block and aninput/output terminal, a fuse array configured to store and to transmitrepair information through the global line, and a control unitconfigured selectively enable or disable a signal paths among theinput/output terminal, the global line, and the fuse array according toan operation mode of the semiconductor apparatus.

In an embodiment, a semiconductor apparatus may include a global lineconfigured to enable electrical coupling between a memory block and aninput/output terminal, a fuse array configured to one of store repairinformation in response to a plurality of control signals and totransmit previously stored repair information, a plurality of switchesconfigured to enable electrical coupling between the fuse array and anode of the global line, between the node and the memory block, andbetween the node and the input/output terminal, and a control unitconfigured to determine an operation mode of the semiconductor apparatusin response to the plurality of control signals, and manage theplurality of switches according to the determined operation mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram representation of an embodiment of asemiconductor apparatus with a repair information control function;

FIG. 2 is a circuit diagram representation of an embodiment of amultiplexing unit of FIG. 1;

FIG. 3 is a switch control table used to explain the operation of acontrol unit; and

FIG. 4 is a block diagram representation of a system including anembodiment of a semiconductor apparatus including a repair informationcontrol function.

DETAILED DESCRIPTION

Various embodiments of a semiconductor apparatus with a repairinformation control function will be described with reference to theaccompanying drawings.

As illustrated in FIG. 1, an embodiment of a semiconductor apparatus 100with a repair information control function may include a memory block200, an input/output terminal 300, a fuse array 400, a multiplexing unit500, a latch unit 600, a plurality of switches SW1-SW8, and a controlunit 700.

The memory block 200 may be configured to store data according to awrite operation and output data according to a read operation.

Although not illustrated, the memory block 200 may include a circuitconfiguration for data input/output.

The memory block may include a plurality of memory cells. A subset ofthe plurality of memory cells may include redundant memory cells(hereafter, referred to as redundant cells) for replacing memory cellsthat may have a defect (hereafter, referred to as defective cells).

The input/output terminal 300 may be configured to perform input/outputdata operations with a device external to the semiconductor apparatus.

The input/output terminal 300 may include a plurality of pads. Anexample of such pads are DQ pads.

The memory block 200 and the input/output terminal 300 are configured tobe electrically coupled via global line sets WGIO and RGIO.

WGIO may represent a write global line set for a write operation andRGIO may represent a read global line set for a read operation.

Such a configuration is an example where different global line sets areused for the write operation and the read operation. In alternativeembodiments, a single global line set may be commonly used for both theread operation and the write operation.

The fuse array 400 may be configured to perform a repair informationinput/output operation in response to control signals CMD, Bootact, TM1,TM2.

The control signal CMD may represent a mode register set (MRS) commandbased on a normal mode. The control signal CMD may be received at thesemiconductor apparatus 100 from a device external to the semiconductorapparatus 100.

The control signal Bootact may represent a signal indicating the startof an initialization mode of the semiconductor apparatus, that is, aboot-up mode. The control signal Bootact may be received at thesemiconductor apparatus 100 from a device external to the semiconductorapparatus 100 or internally generated at the semiconductor apparatus100.

The control signal TM1 may represent a test mode signal for designatinga repair information storage operation. The control signal TM1 may bereceived at the semiconductor apparatus 100 from a device external tothe semiconductor apparatus 100.

The control signal TM2 may represent a test mode signal for designatinga repair information output operation. The control signal TM2 may bereceived at the semiconductor apparatus 100 from a device external tothe semiconductor apparatus 100.

An operation of replacing a defective cell of the memory block 200 witha redundant cell may be referred to as a repair operation. The repairoperation involves replacing an address for accessing the defective cellwith an address corresponding to the redundant cell replacing with thedefective cell.

The repair information may include addresses for accessing defectivecells. The repair information may be stored in the fuse array 400.

A repair information storage operation may involve storing repairinformation in the fuse array 400. The repair information outputoperation may involve transmitting the repair information stored in thefuse array 400 to a device or component external to the fuse array 400.

The fuse array 400 may include a plurality of fuses.

The plurality of fuses may include electrical fuses. The electrical fusemay be electrically coupled or decoupled through a rupture operation.

The operation of storing repair information in the fuse array 400 may beperformed as follows: specific fuses in of the fuse array 400 may beaddressed based on repair information received from a device external tothe semiconductor apparatus 100. The fuse array 400 may rupture theaddressed fuses.

The fuse array 400 may be configured to block storage and transmit therepair information in response to the control signal CMD.

The fuse array 400 may be configured to transmit the stored repairinformation in response to the control signal Bootact.

The fuse array 400 may be configured to perform a repair informationstorage operation in response to the control signal TM1.

The fuse array 400 may be configured to transmit the stored repairinformation in response to the control signal TM2.

The multiplexing unit 500 may be configured to electrically couple thewrite global line set WGIO or the read global line set RGIO to the fusearray 400 in response to the control signals Bootact, TM1, TM2.

The multiplexing unit 500 may be configured to electrically decouple thewrite global line set WGIO or the read global line set RGIO from thefuse array 400 in response to the control signals Bootact, TM1, TM2.

The latch unit 600 may be configured to store repair informationreceived from the fuse array 400. The stored repair information may beused for normal operation of the semiconductor apparatus 100 such as forexample, for operations that are performed following the boot-up mode.

Each of the plurality of switches SW1-SW8 may be configured to enablethe passage of signals or to block the passage of signals along anassociated signal path in response to an associated one of a pluralityof switching signals CTRL<1:8>.

The switch SW1 may enable or disable electrical coupling between a nodeA and the input/output terminal 300.

The switch SW5 may enable or disable electrical coupling between a nodeC and the memory block 200.

The switch SW2 may enable or disable electrical coupling between a nodeB and the input/output terminal 300.

The switch SW6 may enable or disable electrical coupling between a nodeD and the memory block 200.

The switch SW3 may enable or disable electrical coupling between thenode A and the multiplexing unit 500.

The switch SW7 may enable or disable electrical coupling between thenode C and the latch unit 600.

The switch SW4 may enable or disable electrical coupling between thenode B and the multiplexing unit 500.

The switch SW8 may enable or disable electrical coupling between thenode D and the latch unit 600.

The write global line set WGIO and the read global line set RGIO are thelongest signal lines in the semiconductor apparatus 100.

Referring to FIG. 1, the distance between the node A and the node C isrelatively substantially longer than the distance between the node A andthe fuse array 400.

The distance between the node B and the node D is relativelysubstantially longer than the distance between the node D and the latchunit 600.

The control unit 700 may be configured to determine an operation mode ofthe semiconductor apparatus in response to the control signals CMD,Bootact, TM1, TM2, and control the signal paths by managing theplurality of switches SW1-SW8 according to the operation mode.

The control unit 700 may be configured to generate the plurality ofswitching signals CTRL<1:8> for managing the plurality of switchesSW1-SW8 in response to the control signals CMD, Bootact, TM1, TM2.

The control unit 700 may be configured to transmit the control signalsCMD, Bootact, TM1, TM2 to the fuse array 400.

As illustrated in FIG. 2, the multiplexing unit 500 may include a NORgate 510, a plurality of inverters 520, 540, 560, and a plurality oftransmission gates 530, 550.

The NOR gate 510 and the inverter 520 may be configured to turn on thetransmission gate 530 when one of the control signals Bootact and TM1 isactivated.

When the transmission gate 530 is turned on, the fuse array 400 and theswitch SW3 may be electrically coupled to each other.

The transmission gate 550 may be turned on when the control signal TM2is activated.

When the transmission gate 550 is turned on, the fuse array 400 and theswitch SW4 may be electrically coupled to each other.

The control unit 700 may be configured to determine an operation mode ofthe semiconductor apparatus 100 in response to the control signals CMD,Bootact, TM1, TM2, and generate the plurality of switching signalsCTRL<1:8> for selectively turning on the plurality of switches SW1-SW8to enable a corresponding signal path.

The control unit 700 may determine whether the semiconductor apparatus100 is operating in a normal mode, in response to the control signalCMD.

The normal mode refers to an operation mode where data exchangeoperations are performed between the memory block 200 and theinput/output terminal 300 during a read/write operation according to thecontrol signal CMD, where the control signal CMD is the MRS command.

The control unit 700 may determine whether the semiconductor apparatus100 is operating in the initialization mode in response to the controlsignal Bootact. The initialization mode is the boot up mode.

The boot-up mode refers to the operation mode where the repairinformation stored in the fuse array 400 is transmitted to the latchunit 600 according to the control signal Bootact before entering thenormal mode.

The control unit 700 may determine whether the semiconductor apparatus100 is operating in the repair information storage mode in response tothe control signal TM1.

The repair information storage mode refers to the operation mode wherean address corresponding to a defective cell that is detected through atest is stored in the fuse array 400.

The control unit 700 may determine whether the semiconductor apparatus100 operating in the repair information output mode in response to thecontrol signal TM2.

The repair information output mode refers to the mode where the repairinformation stored in the fuse array 400 is transmitted to a deviceexternal to the semiconductor apparatus 100.

As illustrated in FIG. 3, the control unit 700 may selectively turn on asubset of the plurality of switches SW1-SW8 where the combination of thesubset of the switches SW1-SW8 that are turned on based on whether thesemiconductor apparatus 100 is operating in the normal mode, the boot-upmode, the repair information storage mode, or the repair informationoutput mode. The combination of the subset of the switches SW1-SW8 thatare turned on define the signal path.

For example, when the semiconductor apparatus 100 is operating in normalmode, the control unit 700 may generate the plurality of switchingsignals CTRL<1:8> as ‘11001100’. The switches SW1, SW2, SW5, and SW6 maybe turned on, and the other switches SW3, SW4, SW7, and SW8 may beturned off in response to the plurality of switching signals CTRL<1:8>as ‘11001100’.

When the semiconductor apparatus 100 is operating in boot-up mode, thecontrol unit 700 may generate the plurality of switching signalsCTRL<1:8> as ‘00100010’. The switches SW3 and SW7 may be turned on, andthe other switches SW1, SW2, SW4, SW5, SW6, and SW8 may be turned off inresponse to the plurality of switching signals CTRL<1:8> as ‘00100010’.

When the semiconductor apparatus 100 is operating in repair informationstorage mode, the control unit 700 may generate the plurality ofswitching signals CTRL<1:8> as ‘10100000’. The switches SW1 and SW3 maybe turned on, and the other switches SW2, SW4, SW5, SW6, SW7, and SW8may be turned off in response to the plurality of switching signalsCTRL<1:8> as ‘10100000’.

When the semiconductor apparatus 100 is operating in the repairinformation output mode, the control unit 700 may generate the pluralityof switching signals CTRL<1:8> as ‘01010000’. The switches SW2 and SW4may be turned on, and the other switches SW1, SW3, SW5, SW6, SW7, andSW8 may be turned off in response to the plurality of switching signalsCTRL<1:8> as ‘01010000’.

Referring to FIGS. 1 to 3, the repair operation of an embodiment of thesemiconductor apparatus 100 will be described below.

When the semiconductor apparatus 100 is operating in normal mode, thecontrol signals Bootact, TM1, and TM2 may be deactivated to a low level.

Since the control signals Bootact, TM1, and TM2 are at the low level,the multiplexing unit 500 may electrically decouple the fuse array 400from the switches SW3 and SW4.

The control unit 700 may generate the plurality of switching signalsCTRL<1:8> in response to the MRS command of the normal mode. Then, fromamong the plurality of switches SW1-SW8, the switches SW1, SW2, SW5, andSW6 may be turned on, and the other switches SW3, SW4, SW7, and SW8 maybe turned off.

While the switches SW1, SW2, SW5, and SW6 are turned on and the otherswitches SW3, SW4, SW7, and SW8 are turned off, a normal signal path maybe formed between the memory block 200 and the input/output terminal 300via the write global line set WGIO, the read global line set RGIO.

The signal path formed between the between the latch unit 600, the writeglobal line set WGIO, the read global line set RGIO, and the fuse array400 may be disabled or blocked.

When the semiconductor apparatus 100 is operating in boot-up mode, thecontrol signal Bootact may be activated at a high level, and the othercontrol signals CMD, TM1, and TM2 may be activated to the low level.

Since the control signal Bootact is activated to the high level, themultiplexing unit 500 may electrically couple the fuse array 400 to theswitch SW3.

The control unit 700 may generate the plurality of switching signalsCTRL<1:8> in response to the control signal Bootact. Then, from amongthe plurality of switches SW1-SW8, the switches SW3 and SW7 may beturned on, and the other switches SW1, SW2, SW4, SW5, SW6, and SW8 maybe turned off.

While the switches SW3 and S7 are turned on and the other switches SW1,SW2, SW4, SW5, SW6, and SW8 are turned off, an initialization signalpath may be formed from the fuse array 400 to the latch unit 600 via themultiplexing unit 500, the switch SW3, the write global line set WGIO,the switch SW7.

The fuse array 400 may transmit the previously stored repair informationto the latch unit 600 in response to the control signal Bootact.

When an external address received at the semiconductor apparatus 100operating in the normal mode, a read/write operation based on theexternal address or a replaced address may be performed based on therepair information stored in the latch unit 600.

When the semiconductor apparatus 100 is operating in the repairinformation storage mode, the control signal TM1 may be activated to thehigh level, and the other control signals CMD, Bootact, and TM2 may bedeactivated to the low level.

Since the control signal TM1 is activated to the high level, themultiplexing unit 500 may electrically couple the fuse array 400 and theswitch SW3.

The control unit 700 may generate the plurality of switching signalsCTRL<1:8> in response to the control signal TM1. Then, from among theplurality of switches SW1-SW8, the switches SW1 and SW3 may be turnedon, and the other switches SW2, SW4, SW5, SW6, SW7, and SW8 may beturned off.

While the switches SW1 and SW3 are turned on and the other switches SW2,SW4, SW5, SW6, SW7, and SW8 are turned off, a repair information storagesignal path may be formed between the fuse array 400 and theinput/output terminal 300, via the multiplexing unit 500, the switchSW3, the write global line set WGIO, and the switch SW1.

Based on repair information received from a device external to thesemiconductor apparatus 100 the fuse array 400 may rupture the fusesassociated with the address to store the repair information. The addressmay be defined by the signal path defined by the ruptured fuses in thefuse array 400.

When the semiconductor apparatus 100 is operating in repair informationoutput mode, the control signal TM2 may be activated to the high level,and the other control signals CMD, Bootact, and TM1 may be deactivatedto the low level.

Since the control signal TM2 is activated to the high level, themultiplexing unit 500 may electrically couple the fuse array 400 and theswitch SW4.

The control unit 700 may generate the plurality of switching signalsCTRL<1:8> in response to the control signal TM2. Thus, from among theplurality of switches SW1-SW8, the switches SW2 and SW4 may be turnedon, and the other switches SW1, SW3, SW5, SW6, SW7, and SW8 may beturned off.

While the switches SW2 and SW4 are turned on and the other switches SW1,SW3, SW5, SW6, SW7, and SW8 are turned off, a repair information outputsignal path may be formed between the fuse array 400 and theinput/output terminal 300 via the multiplexing unit 500, the switch SW4,the read global line set RGIO the switch SW2. The fuse array 400 maytransmit the previously stored repair information to a device externalto the semiconductor apparatus 100 through the input/output terminal 300in response to the control signal TM2.

Referring to FIG. 4, a block diagram representation of a system 1000including an embodiment of a semiconductor memory apparatus 1350 isshown. In an embodiment, the semiconductor memory apparatus 1350 is thesemiconductor apparatus 100 shown in FIG. 1.

An embodiment of the semiconductor memory apparatus 1350 may include aglobal line configured to enable electrical coupling between a memoryblock and an input/output terminal, a fuse array configured to store andto transmit repair information through the global line, and a controlunit configured selectively enable or disable a signal paths among theinput/output terminal, the global line, and the fuse array according toan operation mode of the semiconductor apparatus.

An embodiment of the semiconductor memory apparatus 1350 may include aglobal line configured to enable electrical coupling between a memoryblock and an input/output terminal, a fuse array configured to one ofstore repair information in response to a plurality of control signalsand to transmit previously stored repair information, a plurality ofswitches configured to enable electrical coupling between the fuse arrayand a node of the global line, between the node and the memory block,and between the node and the input/output terminal, and a control unitconfigured to determine an operation mode of the semiconductor apparatusin response to the plurality of control signals, and manage theplurality of switches according to the determined operation mode.

Examples of the semiconductor memory apparatus 1350 include, but are notlimited to, dynamic random access memory, static random access memory,synchronous dynamic random access memory (SDRAM), synchronous graphicsrandom access memory (SGRAM), double data rate dynamic ram (DDR), anddouble data rate SDRAM.

The memory controller 1200 is used in the design of memory devices,processors, and computer systems. The system 1000 may include one ormore processors or central processing units (“CPUs”) 1100. The CPU 1100may be used individually or in combination with other CPUs. While theCPU 1100 will be referred to primarily in the singular, it will beunderstood by those skilled in the art that a system with any number ofphysical or logical CPUs may be implemented

A chipset 1150 may be electrically coupled to the CPU 1100. The chipset1150 is a communication pathway for signals between the CPU 1100 andother components of the system 1000, which may include the memorycontroller 1200, an input/output (“I/O”) bus 1250, and a disk drivecontroller 1300. Depending on the configuration of the system 1000, anyone of a number of different signals may be transmitted through thechipset 1150, and those skilled in the art will appreciate that therouting of the signals throughout the system 1000 can be readilyadjusted without changing the underlying nature of the system.

As stated above, the memory controller 1200 may be electrically coupledto the chipset 1150. The memory controller 1200 can receive a requestprovided from the CPU 1100, through the chipset 1150. In alternateembodiments, the memory controller 1200 may be integrated into thechipset 1150. The memory controller 1200 may be electrically coupled toone or more semiconductor memory apparatuses 1350. The semiconductormemory apparatuses 1350 may be any one of a number of industry standardmemory types, including but not limited to, single inline memory modules(“SIMMs”) and dual inline memory modules (“DIMMs”). Further, the memorydevices 1350 may facilitate the safe removal of the external datastorage devices by storing both instructions and data.

The chipset 1150 may be electrically coupled to the I/O bus 1250. TheI/O bus 1250 may serve as a communication pathway for signals from thechipset 1150 to I/O devices 1410, 1420 and 1430. The I/O devices 1410,1420 and 1430 may include a mouse 1410, a video display 1420, or akeyboard 1430. The I/O bus 1250 may employ any one of a number ofcommunications protocols to communicate with the I/O devices 1410, 1420,and 1430. Further, the I/O bus 1250 may be integrated into the chipset1150.

The disk drive controller 1450 may also be electrically coupled to thechipset 1150. The disk drive controller 1450 may serve as thecommunication pathway between the chipset 1150 and one or more internaldisk drives 1450. The internal disk drive 1450 may facilitatedisconnection of the external data storage devices by storing bothinstructions and data. The disk drive controller 1300 and the internaldisk drives 1450 may communicate with each other or with the chipset1150 using virtually any type of communication protocol, including allof those mentioned above with regard to the I/O bus 1250.

The system 1000 described above in relation to FIG. 4 is merely oneexample of a system employing a semiconductor memory apparatus 1350. Inalternate embodiments, such as cellular phones or digital cameras, thecomponents may differ from the embodiment shown in FIG. 4.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor apparatusdescribed herein should not be limited based on the describedembodiments. Rather, the semiconductor apparatus described herein shouldonly be limited in light of the claims that follow when taken inconjunction with the above description and accompanying drawings.

What is claimed is:
 1. A semiconductor apparatus comprising: a globalline configured to enable electrical coupling between a memory block andan input/output terminal; a fuse array configured to store and totransmit repair information through the global line; and a control unitconfigured to selectively enable or disable signal paths among theinput/output terminal, the global line, and the fuse array according toan operation mode of the semiconductor apparatus.
 2. The semiconductorapparatus according to claim 1, wherein the memory block comprises aplurality of memory cells and the repair information comprises addressinformation for accessing a memory cell having a defect from among theplurality of memory cells.
 3. The semiconductor apparatus according toclaim 1, wherein the control unit is configured to enable a signal pathbetween the input/output terminal and the fuse array via the global linewhen the operation mode is a repair information storage mode.
 4. Thesemiconductor apparatus according to claim 1, wherein the control unitis configured to enable a signal path between the fuse array and theinput/output terminal via the global line when the operation mode is arepair information output mode.
 5. The semiconductor apparatus accordingto claim 1, wherein the control unit is configured to disable a signalpath between the fuse array and the global line when the operation modeis a normal mode.
 6. The semiconductor apparatus according to claim 1,wherein fuses, addressed through the input/output terminal and theglobal line, of the fuse array are ruptured when the operation mode is arepair information storage mode.
 7. The semiconductor apparatusaccording to claim 1, wherein the fuse array is configured to transmitthe repair information from the semiconductor apparatus through theglobal line and the input/output terminal when the operation mode is arepair information output mode.
 8. The semiconductor apparatus accordingto claim 1, wherein the control unit is configured to enable a signalpath from the fuse array to a latch unit in the semiconductor apparatusvia the global line when the operation mode is an initialization mode.9. The semiconductor apparatus according to claim 8, wherein the fusearray is configured to transmit the repair information for storage inthe latch unit through the global line.
 10. A semiconductor apparatuscomprising: a global line configured to enable electrical couplingbetween a memory block and an input/output terminal for datainput/output; a fuse array configured to one of store repair informationin response to a plurality of control signals and to transmit previouslystored repair information; a plurality of switches configured to enableelectrical coupling between the fuse array and a node of the globalline, between the node and the memory block, and between the node andthe input/output terminal; and a control unit configured to determine anoperation mode of the semiconductor apparatus in response to theplurality of control signals, and manage the plurality of switchesaccording to the determined operation mode.
 11. The semiconductorapparatus according to claim 10, wherein the global line comprises awrite global line set for a write operation and a read global line setfor a read operation.
 12. The semiconductor apparatus according to claim10, wherein the plurality of control signals define the operation modeof the semiconductor apparatus as one of a repair information storagemode, a repair information output mode, a normal mode, and aninitialization mode.
 13. The semiconductor apparatus according to claim12, wherein the control unit is configured to manage the plurality ofswitches to enable a signal path between the input/output terminal andthe fuse array via the global line when the operation mode of thesemiconductor apparatus is determined to be the repair informationstorage mode.
 14. The semiconductor apparatus according to claim 12,wherein the control unit is configured to manage the plurality ofswitches to enable a signal path between the fuse array and theinput/output terminal via the global line when the operation mode of thesemiconductor apparatus is determined to be the repair informationoutput mode.
 15. The semiconductor apparatus according to claim 12,wherein the control unit is configured to manage the plurality ofswitches to disable a signal path between the fuse array and the globalline when the operation mode of the semiconductor apparatus isdetermined to be the normal mode.
 16. The semiconductor apparatusaccording to claim 12, further comprising a latch unit configured tostore repair information associated with the normal mode.
 17. Thesemiconductor apparatus according to claim 16, wherein the control unitis configured to manage the plurality of switches to enable a signalpath between the fuse array and the latch unit via the global line whenthe operation mode of the semiconductor apparatus is determined to bethe initialization mode.
 18. The semiconductor apparatus according toclaim 12, wherein the fuse array is configured to rupture fusesaddressed through the input/output terminal and the global line when thecontrol signal associated with the repair information storage mode isactivated.
 19. The semiconductor apparatus according to claim 12,wherein the fuse array is configured to transmit previously storedrepair information when the control signal associated with one of theinitialization mode and repair information output mode is activated. 20.The semiconductor apparatus according to claim 10, wherein the memoryblock comprises a plurality of memory cells and the repair informationcomprises address information for accessing a memory cell having adefect from among the plurality of memory cells.